NVRAM Accelerator

Caching, Write-Ahead Logging, Journaling


  • Over 1.3 Mil. IOPS – 4K Random Writes
  • Over 5.5GB/s – 128K Random Writes
  • Support for block transfers using the NVMe
    command set or mmap byte addressable PIO
  • 8GB and 16GB capacities
  • Half-Height, Half-Length (HHHL)
  • On-board capacitors – no cabling to remote power packs


The RMS-300 is visible as a standard block device that supports DMA operations with the NVMe command set, and can also be memory mapped for 4 byte (dword) direct Programmed I/O accesses.  With exceptional, consistent performance for small random writes and unlimited write endurance, the RMS-300 is an ideal solution for intent logs, journaling, or any metadata operations requiring low latency persistent storage.

NVMe PCIe x8 Gen3


nvm_express_color                           pci-sig

Upon system power failure, the RMS-300 switches to an auxiliary power mode provided by on-board ultracapacitors and data that is stored in volatile DRAM is transferred to persistent NAND memory by the Flush-to-Flash firmware. Once transferred to NAND memory, data is stored in the persistent
storage and not vulnerable to the 72-hour limitations common to battery-based architectures that hold data in volatile DRAM in a self-refresh mode. Radian’s Flush-to-Flash firmware is based on transactional semantics to ensure the utmost in data integrity even in the event of most potential failures that could occur during the flush process.



1434855273_FEZ-03 RMS-300 Data Sheet

Extensive monitoring and component checks are performed on an on-going basis during normal operations to discover predictive anomalies in advance of failures. NAND Flash memory is regularly scanned for potential errors (bad blocks) and ultracapacitor health is monitored on a continual basis. However, in the event of a failure during the flush process, such as a lack of power required to perform a complete data transfer, the Flush-to-Flash system ensures that partial data is properly transferred and can be identified accordingly upon restore. A hardware LDPC engine in the controller provides error correction functionality with 10-17 UBER and, combined with the firmware implementation, protects data against NAND page or block errors. Extensive use of metadata and error checking is performed on all data upon restore to ensure correctness.

The overall Flush-to-Flash system and underlying NAND array are based on a fault tolerant architecture, including overprovisioning resources such as ultracapacitor power and NAND capacity, to address events such as repeated system power blackouts and brownouts. The architecture and design verification test processes further address these conditions in the context of operations such as concurrent host atomic writes, providing the highest levels of enterprise reliability.